The present subject matter relates to a semiconductor device, and more particularly, to a dynamic random access memory (DRAM) architecture.
A DRAM uses a time multiplexed addressing method. A row address is latched when a row address strobe (RAS) signal is inputted, and a column address is latched when a column address strobe (CAS) signal is inputted. When the RAS signal is inputted, a predetermined memory cell array is selected and a word line driver and a sense amplifier are enabled. When the CAS signal is inputted, a read or write operation is determined. A column address to be accessed is latched and a location of data to be inputted/outputted is finally determined.
Generally, before the CAS signal is inputted, a memory cell array of a DRAM cannot determine a location of a memory cell to be accessed. Further, the DRAM must obey a time difference (tRCD) between the RAS signal and the CAS signal. The time difference (tRCD) is required to ensure a time necessary to enable the word line and the sense amplifier.
In other words, a conventional DRAM has a time difference between a row addressing timing for enabling the memory cell array and a column addressing timing for determining the final location of the memory cell.
Since the conventional DRAM cannot determine the final memory cell array at the row addressing timing, the sense amplifier array of the memory cell array is enabled to serve as a row cache. At this point, the predefined number of the cell arrays is called a page size. The page size is determined by the number of column addresses.
Specifically, memory cell arrays of one page are enabled in response to the RAS signal. Thereafter, a column address is provided for determining a location of data to be finally inputted/outputted in response to the CAS signal.
However, the conventional DRAM has a structural problem in that one page is enabled regardless of the size of data which will be finally inputted/outputted during one access cycle, thus causing an excessive power consumption.